A description for high-speed communication networks for the 21st century is roughly sketched, and the technical development trends in high-frequency and high-speed devices are briefly forecasted. Four examples of devices under development are reported: 76-GHz flip-chip MMIC's for car-radar systems, a cost-effective RF module for millimeter-wave wireless systems, a 10-Gbps demultiplexer for optical fiber communication systems, and a GaAs microwave signal processor for active phased-array systems. Considering as technological trends evolve further, this paper also introduces the software radio concept and the fusion of wireless and optical technologies for cost-effective wireless communication equipment and end-user services.

A new data-I/O scheme with a hidden writing-recovery architecture has been developed for the megabit-class high operating frequency SRAMs. Read-out nodes in the memory cell are separated from bitline-connected writing nodes so as not to delay sensing initiation due to uncompleted bitline recovery. The data stored in a memory cell are read-out by sensing the differential current signal on a double-rail virtual-GND line along bitlines. Each pair of virtual-GND lines is imaginarily short-circuited by a sense amplifier, so that the read-out circuitry would have large immunity against virtual-GND-line noises. The critical noise level associated with data destruction is analyzed at various supply voltages. The virtual-GND-line-sensed memory cell with the squashed topology, the swing-suppression-type low-power writing circuitry, and the current-sense amplifier with extra negative feedback loops, --which are used in the data-I/O scheme are also mentioned. Assuming a sub array in megabit-class SRAMs, 4 K-words 6 -bits test chip was fabricated with a 0.5-µm CMOS process. The SRAM achieved 180-MHz operation at a typical 3.3-V, 25 condition. The power dissipation at the practical operating frequency of 133-MHz was 50-mW.

In this paper, we present a simple codeword length generation algorithm and its hardware implementation. The proposed technique is based on the dividing the Huffman table as two parts; with leading 0'bits and following bits. The method is shown to be efficient in the memory requirement and searching speed since only logic gates are needed in the implementation and searching can be process parallel without looking up the memory table. The total equivalent gates for the implementation are about only 100 gates and critical path delay is 10 ns. The results of experiments show that the proposed algorithm has a very high speed and a good performance. The designed blocks are synthesized by Compass synthesis with 0.5 µm CMOS, 3.3V, technology.

This paper describes a newly developed FET Coupled Logic (FCL) circuit that operates at very high frequencies with very low supply voltages below 3.3 V. An FCL circuit consists of NMOS source-coupled transistor pairs for current switches, load resistors, emitter followers and current sources that are controlled by a band-gap reference bias generator. The characteristics and performance are discussed by comparing this circuit with other high-speed circuits. The optimal circuit parameters for FCL circuits are also discussed, and the fact is noted that a larger swing voltage enhances the circuit's performance. The simulated delay of a 0.25 µm FCL circuit is less than 15 ps for a 2.5 V power supply, and the simulated maximum toggle frequencies are over 5 GHz and 10 GHz at 2.5 V and 3.3 V power supply, respectively. The simulation results show that FCL circuits achieve the best performance among the current mode circuits, which include ECL circuits, NMOS source-coupled logic circuits. The delay of the FCL circuit is less than half that of an ECL circuit. The maximum toggle frequency of the FCL circuit is about triple that of NMOS source-coupled logic circuit. Because the FCL circuit uses low-cost CMOS-based BiCMOS technologies, its cost performance is superior to ECL circuits that require expensive base-emitter self-aligned processes and trench isolation processes. Using depletion-mode NMOS transistors for current switches can lower the minimum supply voltage for FCL circuits and it is below 1.5 V. The FCL circuit is a promising logic gate circuit for multi-Gbit/s tele/data communication LSIs.

It is confirmed by simulation that SOI-DRAMs can be operated at high speed by using the floating body structures. Several floating body effects are analyzed. It is described that the dynamic retention characteristics are not dominated by capacitive coupling and hole redistribution. And it is described that those characteristics are determined by the leakage current in the small pn-junction region of the floating body. Reducing pn junction leakage current is important for realizing a long retention time. If the pn junction leakage is suppressed to 10-18 A/µm, a dynamic retention time of 520 sec at a VBSG of 0.5 V can be achieved at 27. On those conditions, the refresh current of SOI-DRAMs is reduced by 54% compared with bulk-Si DRAMs.

The distributions of a spectral intensity of the breaking arc between silver contacts in DC 45-66 V/2.5-5.0 A circuits have been measured using a high-speed color video. As a result, a cathode brightening spot, which has a high spectral intensity, exists near the cathode surface. The cathode brightening spot expands with the increase of the contact gap, but its length expands until about 18µm. When the contact gap spreads over about 180 µm, a dark positive column appears and grows between the cathode brightening spot and the anode surface. The higher the interrupted current is, the larger the diameter of the cathode brightening spot will be. The maximum diameter of cathode brightening spot is 500 µm under these experiments.

High-speed and low-power techniques are described for megabit-class size-configurable CMOS SRAM macrocells. To shorten the design turn-around-time, the methodology of abutting nine kinds of leaf cells is employed; two-level via-hole programming and the array-address decoder embedded in each control leaf cell present a divided-memory-array structure. A new squashed-memory-cell architecture using trench isolation and stacked-via-holes is proposed to reduce access times and power dissipation. To shorten the time for writing data, per-bitline architecture is proposed, in which every bitline has a personal writing driver. Also, read-out circuitry using a current-sense-type two-stage sense amplifier is designed. The effect of the non-multiplexed bitline scheme for fast read-out is shown in a simulation result. To reduce the noise from the second- to first-stage amplifier due to a feedback loop, current paths are separated so as not to cause common impedance. To confirm the techniques described in this paper, a 1-Mb SRAM test chip was fabricated with an advanced 0.35-µm CMOS/bulk process. The SRAM has demonstrated 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power dissipation was obtained at a practical operating frequency of 150-MHz.

MTDMA (Multimedia, Multimode TDMA) system has been developed for the 3rd generation mobile communications. An adaptive modulation technique is employed, which select 16 QAM or QPSK modulations fit for the O (Indoor Office)/P (Outdoor to Indoor and Pedestrian) communication environments. The maximum user rate of 4 Mbps is realized. Basic specification is described for O, P and V environments.

Ferroelectric non-volatile memory (FeRAM) has been inspiring interests since bismuth layer perovskite material family was found to provide "Fatigue Free" endurance, superior retention and imprint characteristics. In this paper, we will provide new circuits technology for FeRAM developed to implement high speed operation, low voltage operation and low power consumption. Performance of LSI embedded with FeRAM for contactless IC card is also provided to demonstrate the feasibility of the circuit technology.

The location of stations on the buses can not be ignored in the analysis of the DQDB protocol, especially when traffic load is heavy. In this paper, we propose a new method to model the DQDB (Distributed Queue Dual Bus) protocol by assuming that the request arrival process depends on both the value of the request counter and the location of a station on the buses. By taking these dependences, we can catch the real behavior of the DQDB stations, which is locationally dependent and unfair under heavy load traffic. Based on this model, we analyze the DQDB system with finite buffer by considering the request counter states and buffer states separately and obtain the throughput, mean packet delay and packet reject probability of individual stations. The throughput in individual stations matches that of simulation very well within the range of traffic up to the channel capacity. Also the delay and packet reject rate performance is good up to moderate traffic load. These numerical results reveal the properties of the location dependence and the unfairness of DQDB system under heavy load condition. The analytic results under heavy load traffic for a general DQDB system has not been reported till now. Therefore we conclude that our model and analysis are valid and effective.

This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.

A 100MIPS high speed and low power fixed point Digital Signal Processor (DSP) has been developed applying 0.45µm CMOS TLM technology. The DSP contains a 16-bit32K full CMOS static RAM with a hierarchical low power architecture. The device is a RAM based DSP with a total of 4.2 million transistors and a new low power design and process which enabled an approximate 50% reduction in power as compared to conventional DSPs at 40 MHz. In order to cover very wide application requirements, this DSP is capable of operating at 1.0 V for DSP core and 3.3 V for I/O. This was achieved by new level shifter circuitry to interface with cost effective 3 V external commodity products and confirmed 80% of power reduction at Core VDD=2.0 V, I/O VDD=3.3 V at 40MHz. This paper describes the new features of the high speed and low power DSP.

This paper describes the design and architecture for a newly developed microprocessor suitable for consumer applications, which we call SuperH. To achieve both low-power and high-speed, the SuperH architecture includes 16-bit fixed length instruction code and several power saving features. The 16-bit fixed length instruction code makes the SuperH possible to achieve excellent code efficiency for the SPECint benchmarks when compared with conventional microcontrollers and RISC's for workstations and PC's. As a result, the SuperH provides almost the same code efficiency as that of 8-bit microcontrollers, and also achieves similar performance as that of RISC's with 32-bit fixed length instruction code. The SuperH also incorporates several power reduction techniques through the control of clock frequency and clock distribution. Thus, the 16-bit code format, power saving features, and other architectural innovations make the SuperH particularly proficient for portable multi-media applications.

This paper surveys low-power design techniques for Si bipolar Gbit/s LSIs. First, a total strategy for power reduction in bipolar LSIs is described. The power dissipation of Si bipolar LSIs can be minimized by reducing the supply voltage, switching and driving currents, the power of input and output circuits, and the equivalent "on" ratio. Widely spread activities from device to architecture levels are indispensable and each of the low-power techniques reduces power by a factor of about 0.5 to 0.7. The integration of these techniques is very important, and as a certain example of their effectiveness, an SOH signal processing LSI is demonstrated with a reduction factor of 1/10. Comparisons with other device technologies for low power characteristics reveal the low-power potential of bipolar LSIs in the Gbit/s region.

In this paper, we consider conventional signaling link fault tolerance and error correction mechanisms to provide reliable services of mobile multimedia telecommunication network based on ATM (Asynchronous Transfer Mode) technology. Also, we propose an efficient signaling protocol interworking architecture and a reliable distributed interworking network architecture between SS7 based FPLMTS and ATM networks. Besides, we evaluate the performance of proposed method through computer simulation. According to the results, proposed signaling architecture shows efficient and fast fault restoration characteristics than conventional MTP-3/3b based network. Functional signaling protocol stack and network architecture of proposed fast rerouting mechanism provide reliable and efficient restoration performance in view of interworking between SS7 based FPLMTS and ATM networks.

A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-µm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5 V and an ambient temperature of 75. The same margins 1.1 ns of the setup time and hold time were measured for the specifications of a setup time of 2.0 ns and a hold time of 0.5 ns.

The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.

Progress made in the field of high speed networking technology has led to the planning and prototyping of true high-bandwidth applications with very high throughput and low delay requirements. In this study we approach the problem of high throughput demand from the aspect of protocols and introduce the handling of error control in the application layer level as opposed to the transport layer since the eventual destination of data is the application itself. This scheme, called ACER (Application Conscious Error Recovery), is proposed and defined for bulk data transfers. A simple analytic throughput comparison of the sliding window scheme with go-back-N, and ACER is given later, Also, a prototype implementation of ACER for bulk data transfer and experimental measurement results are presented. Besides, we investigate the performance of the scheme by simulation for various network models. Finally, we present a discussion of extending the scheme to different traffic patterns and applications.

The up and coming multimedia services are based on real-time high-speed networks. For efficient operation of such services, real-time and precise network management is essential. In this paper, we show that presently available MIB designs are severely inadequate to support real-time network management. We point out and analyze the management constraints and bottlenecks. The concept of quality of management of management information is introduced and its importance in practical network management is discussed. We have proposed a new MIB architecture that will raise the quality of management information to meet the requirements of managing high-speed networks and multimedia services. Experimental results from a prototype implementation of the new MIB architecture are presented.

This paper reports a 32k32 1-Mbit CMOS synchronous pipelined burst SRMA. A clock access time of 3.6 ns and a minimum cycle time of 9 ns(111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 µA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.